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| Freescale Semiconductor, Inc. Technical Data MC145170-2/D Rev. 4, 02/2003 PLL Frequency Synthesizer with Serial Interface MC145170-2 P SUFFIX CASE 648 D SUFFIX CASE 751B DT SUFFIX CASE 948C Freescale Semiconductor, Inc... Ordering Information Device MC145170P2 MC145170D2 MC145170DT2 TA = -40 to 85C Operating Temp Range Package Plastic DIP SOG-16 TSSOP-16 Contents: 1 2 3 4 5 Introduction . . . . . . . . . . 1 Specifications . . . . . . . . 3 Pin Connections . . . . . 10 Design Considerations 18 Packaging. . . . . . . . . . . 30 1 Introduction The new MC145170-2 is pin-for-pin compatible with the MC145170-1. A comparison of the two parts is shown in the table below. The MC145170-2 is recommended for new designs and has a more robust power-on reset (POR) circuit that is more responsive to momentary power supply interruptions. The two devices are actually the same chip with mask options for the POR circuit. The more robust POR circuit draws approximately 20 A additional supply current. Note that the maximum specification of 100 A quiescent supply current has not changed. The MC145170-2 is a single-chip synthesizer capable of direct usage in the MF, HF, and VHF bands. A special architecture makes this PLL easy to program. Either a bit- or byteoriented format may be used. Due to the patented BitGrabber registers, no address/steering bits are required for random access of the three registers. Thus, tuning can be accomplished via a 2-byte serial transfer to the 16-bit N register. The device features fully programmable R and N counters, an amplifier at the fin pin, on-chip support of an external crystal, a programmable reference output, and both single- and doubleended phase detectors with linear transfer functions (no dead zones). A configuration (C) register allows the part to be configured to meet various applications. A patented feature allows the C register to shut off unused outputs, thereby minimizing noise and interference. In order to reduce lock times and prevent erroneous data from being loaded into the counters, a patented jam-load feature is included. Whenever a new divide ratio is loaded into the N register, both the N and R counters are jam-loaded with their respective values and begin counting down together. The phase detectors are also initialized during the jam load. * Operating Voltage Range: 2.7 to 5.5 V (c) Motorola, Inc., 2003. All rights reserved. For More Information On This Product, Go to: www.freescale.com Introduction Freescale Semiconductor, Inc. * Maximum Operating Frequency: 185 MHz @ Vin = 500 mVpp, 4.5 V Minimum Supply 100 MHz @ Vin = 500 mVpp, 3.0 V Minimum Supply Operating Supply Current: 0.6 mA @ 3.0 V, 30 MHz 1.5 mA @ 3.0 V, 100 MHz 3.0 mA @ 5.0 V, 50 MHz 5.8 mA @ 5.0 V, 185 MHz Operating Temperature Range: -40 to 85C R Counter Division Range: 1 and 5 to 32,767 N Counter Division Range: 40 to 65,535 Direct Interface to Motorola SPI Serial Data Port See Application Notes AN1207/D and AN1671/D Contact Motorola for MC145170 control software. Table 1. Comparision of the PLL Frequency Synthesizers Parameter Minimum Supply Voltage Maximum Input Current, fin Dynamic Characteristics, fin (Figure 26) Power-On Reset Circuit MC145170-2 2.7 V 150 A Unchanged Improved MC145170-1 2.5 V 120 A - * * * * * * * Freescale Semiconductor, Inc... 2 MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Electrical Characteristics OSCin OSCout 1 2 OSC 15-stage R Counter fR Control 9 fR 15 REFout 3 4-Stage Reference Divider 3 BitGrabber R Register 15 Bits Lock Detector and Control 11 LD CLK Din Dout 7 5 Shift Register And Control Logic BitGrabber C Register 8 Bits 16 Phase/Frequency Detector A and Control 13 PDout 8 POR Freescale Semiconductor, Inc... ENB 6 BitGrabber N Register 16 Bits 16 Phase/Frequency Detector B and Control 14 15 fR fV fV Control fin 4 Input AMP 16-Stage N Counter Pin 16 = VDD Pin 12 = VSS 10 fV This device contains 4,800 active transistors. Figure 1. Block Diagram 2 Electrical Characteristics Table 2. Maximum Ratings (Voltages Referenced to VSS) Parameter DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VDD and VSS Pins Power Dissipation, per Package Storage Temperature Lead Temperature, 1 mm from Case for 10 seconds Symbol VDD Vin Vout Iin Iout IDD PD Tstg TL Value -0.5 to 5.5 -0.5 to VDD + 0.5 -0.5 to VDD + 0.5 10 20 30 300 -65 to 150 260 Unit V V V mA mA mA mW C C NOTES: 1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section. 2. ESD data available upon request. MOTOROLA MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com 3 Electrical Characteristics Freescale Semiconductor, Inc. (Voltages Referenced to VSS, TA = -40 to 85C) Table 3. Electrical Characteristics Parameter Power Supply Voltage Range Maximum Low-Level Input Voltage [Note 1] (Din, CLK, ENB, fin) Minimum High-Level Input Voltage [Note 1] (Din, CLK, ENB, fin) Minimum Hysteresis Voltage (CLK, ENB) Maximum Low-Level Output Voltage (Any Output) Minimum High-Level Output Voltage (Any Output) Minimum Low-Level Output Current (PDout, REFout, fR, fV, LD, R, V) Minimum High-Level Output Current (PDout, REFout, fR, fV, LD, R, V) Minimum Low-Level Output Current (Dout) Minimum High-Level Output Current (Dout) Maximum Input Leakage Current (Din, CLK, ENB, OSCin) Maximum Input Current (fin) Maximum Output Leakage Current (PDout) (Dout) Maximum Quiescent Supply Current Iout = 20 A Iout = - 20 A Vout = 0.3 V Vout = 0.4 V Vout = 0.5 V Vout = 2.4 V Vout = 4.1 V Vout = 5.0 V Vout = 0.4 V Vout = 4.1 V Vin = VDD or VSS Vin = VDD or VSS Test Condition Symbol VDD VIL VDD V 2.7 4.5 5.5 2.7 4.5 5.5 2.7 5.5 2.7 5.5 2.7 5.5 2.7 4.5 5.5 2.7 4.5 5.5 4.5 Guaranteed Limit 2.7 to 5.5 0.54 1.35 1.65 2.16 3.15 3.85 0.15 0.20 0.1 0.1 2.6 5.4 0.12 0.36 0.36 -0.12 -0.36 -0.36 1.6 Unit V V dc Coupling to fin VIH dc Coupling to fin VHys VOL VOH IOL V V Freescale Semiconductor, Inc... V V mA IOH mA IOL IOH Iin Iin IOZ mA 4.5 -1.6 1.0 150 mA A A 5.5 5.5 Vin = VDD or VSS, Output in High-Impedance State Vin = VDD or VSS; Outputs Open; Excluding fin Amp Input Current Component 5.5 5.5 IDD 5.5 100 5.0 100 nA A A NOTES: 1. When dc coupling to the OSCin pin is used, the pin must be driven rail-to-rail. In this case, OSC out should be floated. 2. The nominal values at 3.0 V are 0.6 mA @ 30 MHz, and 1.5 mA @ 100 MHz. The nominal values at 5.0 V are 3.0 mA @ 50 MHz, and 5.8 mA @ 185 MHz. These are not guaranteed limits. 4 MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Electrical Characteristics Table 3. Electrical Characteristics (Continued) (Voltages Referenced to VSS, TA = -40 to 85C) Parameter Maximum Operating Supply Current Test Condition Symbol Idd VDD V Guaranteed Limit [Note 2] Unit mA fin = 500 mVpp; OSCin = 1.0 MHz @ 1.0 Vpp; LD, fR, fV, REFout = Inactive and No Connect; OSCout, V, R, PDout = No Connect; Din, ENB, CLK = VDD or VSS Freescale Semiconductor, Inc... NOTES: 1. When dc coupling to the OSCin pin is used, the pin must be driven rail-to-rail. In this case, OSC out should be floated. 2. The nominal values at 3.0 V are 0.6 mA @ 30 MHz, and 1.5 mA @ 100 MHz. The nominal values at 5.0 V are 3.0 mA @ 50 MHz, and 5.8 mA @ 185 MHz. These are not guaranteed limits. Table 4. AC Interface Characteristics ( TA = -40 to 85C, CL = 50 pF, Input tr = tf = 10 ns, unless otherwise noted.) Parameter Symbol fclk Figure No. 2 VDD V 2.7 4.5 5.5 2.7 4.5 5.5 2.7 4.5 5.5 2.7 4.5 5.5 2.7 4.5 5.5 2.7 4.5 5.5 Guaranteed Limit dc to 3.0 dc to 4.0 dc to 4.0 150 85 85 300 200 200 0 to 200 0 to 100 0 to 100 150 50 50 900 150 150 10 10 Unit MHz Serial Data Clock Frequency (Note: Refer to Clock tw Below) tPLH, tPHL Maximum Propagation Delay, CLK to Dout tPLZ, tPHZ 2, 6 ns Maximum Disable Time, Dout Active to High Impedance 3, 7 ns tPZL, tPZH Access Time, Dout High Impedance to Active Maximum Output Transition Time, Dout CL = 50 pF tTLH, tTHL 3, 7 ns 2, 6 ns CL = 200 pF 2, 6 ns Maximum Input Capacitance - Din, ENB, CLK Maximum Output Capacitance - Dout Cin Cout pF pF MOTOROLA MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com 5 Electrical Characteristics Freescale Semiconductor, Inc. Table 5. Timing Requirements (TA = -40 to 85C, Input tr = tf = 10 ns, unless otherwise noted.) Parameter Symbol tsu, th Minimum Setup and Hold Times, Din vs CLK tsu, th, trec 5 Figure No. 4 VDD V 2.7 4.5 5.5 2.7 4.5 5.5 2.7 4.5 5.5 2.7 4.5 5.5 2.7 4.5 5.5 Guaranteed Limit 55 40 40 135 100 100 400 300 300 166 125 125 100 100 100 Unit ns Minimum Setup, Hold, and Recovery Times, ENB vs CLK ns tw(H) Minimum Inactive-High Pulse Width, ENB 5 ns Freescale Semiconductor, Inc... tw Minimum Pulse Width, CLK 2 ns t r, t f Maximum Input Rise and Fall Times, CLK 2 s 6 MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Electrical Characteristics 2.1 Switching Waveforms tf 90% CLK 50% 10% tw 1/fclk tPLH Dout 90% 50% 10% tTLH tTHL tPHL tw tr VDD VSS VDD ENB 50% VSS tPZL Dout 50% tPZH Dout 50% tPHZ 90% VSS High Impedance tPLZ 10% High Impedance VDD Figure 2. Figure 3. tw(H) VDD Freescale Semiconductor, Inc... Valid Din 50% VSS tsu CLK th 50% VSS VDD VDD VSS ENB 50% tsu 50% First CLK Last CLK VSS th trec VDD CLK Figure 4. Test Point Figure 5. Test Point 7.5 k Device Under Test CL* Device Under Test CL* Connect to VDD when testing tPLZ AND tPZL. Connect to VSS when testing tPHZ and tPZH. * Includes all probe and fixture capacitance. *Includes all probe and fixture capacitance. Figure 6. Test Circuit Figure 7. Test Circuit MOTOROLA MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com 7 Electrical Characteristics Freescale Semiconductor, Inc. Table 6. Loop Specifications (TA = -40 to 85C) Figure No. 8 VDD V 2.7 3.0 4.5 5.5 Guaranteed Range Unit Min 5.0 5.0 25 45 Max 80 100 185 185 MHz Parameter Test Condition Symbol Input Frequency, fin [Note} Vin 500 mVpp Sine Wave, N Counter Set to Divide Ratio Such that fV 2.0 MHz Vin 1.0 Vpp Sine Wave, OSCout = No Connect, R Counter Set to Divide Ratio Such that fR 2 MHz C1 30 pF C2 30 pF Includes Stray Capacitance f f 9 Input Frequency, OSCin Externally Driven with ac-coupled Signal 2.7 3.0 4.5 5.5 1.0* 1.0* 1.0* 1.0* 22 25 30 35 MHz Freescale Semiconductor, Inc... fXTAL 11 Crystal Frequency, OSCin and OSCout 2.7 3.0 4.5 5.5 2.7 4.5 5.5 2.7 4.5 5.5 2.0 2.0 2.0 2.0 dc dc dc dc dc dc 20 16 - 12 12 15 15 10 10 2.0 2.0 100 90 65 60 7.0 7.0 MHz Output Frequency, REFout Operating Frequency of the Phase Detectors Output Pulse Width, R, V, and LD Output Transition Times, R, V, LD, fR, and fV Input Capacitance fin OSCin fout CL = 30 pF f 12, 14 MHz MHz fR in Phase with fV CL = 50 pF tw 13, 14 2.7 4.5 5.5 2.7 4.5 5.5 - ns CL = 50 pF tTLH, tTHL Cin 13, 14 ns - pF * IF lower frequency is desired, use wave shaping or higher amplitude sinusoidal signal in ac-coupled case. Also, see Figure 25 for dc coupling. Sine Wave Generator 100 pF fin Vin 50 * VSS VDD V+ fV Test Point MC145170-2 *Characteristic impedance Figure 8. Test Circuit, fin 8 MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Electrical Characteristics 0.01 F OSCin 5.0 M 50 Vin MC145170-2 OSCout VSS VDD V+ fR Test Point Sine Wave Generator V+ 1.0 M Sine Wave Generator 0.01 F OSCin Vin 50 1.0 M fR Test Point MC145170-2 OSCout VSS VDD V+ No Connect Freescale Semiconductor, Inc... Figure 9. Test Circuit, OSC Circuitry Externally Driven [Note] Figure 10. Circuit to Eliminate Self-Oscillation, OSC Circuitry Externally Driven [Note] NOTE: Use the circuit of Figure 10 to eliminate self-oscillation of the OSCin pin when the MC145170-2 has power applied with no external signal applied at Vin. (Self-oscillation is not harmful to the MC145170-2 and does not damage the IC.) OSCin C1 MC145170-2 REFout C2 OSCout VSS VDD Test Point 1/f REFout REFout 50% V+ Figure 11. Test Circuit, OSC Circuit with Crystal Figure 12. Test Circuit Test Point tw Output 50% 90% 10% tTHL Output Device Under Test tTLH CL* *Includes all probe and fixture capacitance. Figure 13. Switching Waveform Figure 14. Test Load Circuit MOTOROLA MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com 9 Pin Connections Freescale Semiconductor, Inc. 3 Pin Connections 3.1 Digital Interface Pins Din Serial Data Input (Pin 5) The bit stream begins with the most significant bit (MSB) and is shifted in on the low-to-high transition of CLK. The bit pattern is 1 byte (8 bits) long to access the C or configuration register, 2 bytes (16 bits) to access the N register, or 3 bytes (24 bits) to access the R register. Additionally, the R register can be accessed with a 15-bit transfer (see Table 7). An optional pattern which resets the device is shown in Figure 15. The values in the C, N, and R registers do not change during shifting because the transfer of data to the registers is controlled by ENB. Freescale Semiconductor, Inc... The bit stream needs neither address nor steering bits due to the innovative BitGrabber registers. Therefore, all bits in the stream are available to be data for the three registers. Random access of any register is provided (i.e., the registers may be accessed in any sequence). Data is retained in the registers over a supply range of 2.7 to 5.5 V. The formats are shown in Figures 15, 16, 17, and 18. Din typically switches near 50% of VDD to maximize noise immunity. This input can be directly interfaced to CMOS devices with outputs guaranteed to switch near rail-to-rail. When interfacing to NMOS or TTL devices, either a level shifter (MC74HC14A, MC14504B) or pull-up resistor of 1 to 10 k must be used. Parameters to consider when sizing the resistor are worst-case IOL of the driving device, maximum tolerable power consumption, and maximum data rate. Table 7. Register Access (MSBs are shifted in first, C0, N0, and R0 are the LSBs) Number of Clocks 9 to 13 8 16 15 or 24 Other Values 32 Values > 32 Accessed Register See Figure 15 C Register N Register R Register None See Figures 27 to 34 Bit Nomenclature (Reset) C7, C6, C5, ..., C0 N15, N14, N13, ..., N0 R14, R13, R12, ..., R0 CLK Serial Data Clock Input (Pin 7) Low-to-high transitions on Clock shift bits available at Din, while high-to-low transitions shift bits from Dout. The chip's 16-1/2-stage shift register is static, allowing clock rates down to dc in a continuous or intermittent mode. Four to eight clock cycles followed by five clock cycles are needed to reset the device; this is optional. Eight clock cycles are required to access the C register. Sixteen clock cycles are needed for the N register. Either 15 or 24 cycles can be used to access the R register (see Table 7 and Figures 15, 16, 17, and 18). For cascaded devices, see Figures 27 to 34. CLK typically switches near 50% of VDD and has a Schmitt-triggered input buffer. Slow CLK rise and fall times are allowed. See the last paragraph of Din for more information. NOTE: To guarantee proper operation of the power-on reset (POR) circuit, the CLK pin must be held at the potential of either the VSS or VDD pin during power up. That is, the CLK input should not be floated or toggled while the VDD pin is ramping from 0 to at least 2.7 V. If control of the CLK pin is not practical during power up, the initialization sequence shown in Figure 15 must be used. 10 MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. ENB Active-Low Enable Input (Pin 6) Pin Connections This pin is used to activate the serial interface to allow the transfer of data to/from the device. When ENB is in an inactive high state, shifting is inhibited, Dout is forced to the high-impedance state, and the port is held in the initialized state. To transfer data to the device, ENB (which must start inactive high) is taken low, a serial transfer is made via Din and CLK, and ENB is taken back high. The low-to-high transition on ENB transfers data to the C, N, or R register depending on the data stream length per Table 7. NOTE: Transitions on ENB must not be attempted while CLK is high. This puts the device out of synchronization with the microcontroller. Resynchronization occurs when ENB is high and CLK is low. This input is also Schmitt-triggered and switches near 50% of VDD, thereby minimizing the chance of loading erroneous data into the registers. See the last paragraph of Din for more information. Dout Three-State Serial Data Output (Pin 8) Freescale Semiconductor, Inc... Data is transferred out of the 16-1/2-stage shift register through Dout on the high-to-low transition of CLK. This output is a No Connect, unless used in one of the manners discussed below. Dout could be fed back to an MCU/MPU to perform a wrap-around test of serial data. This could be part of a system check conducted at power up to test the integrity of the system's processor, PC board traces, solder joints, etc. The pin could be monitored at an in-line QA test during board manufacturing. Finally, Dout facilitates troubleshooting a system and permits cascading devices. 3.2 Reference Pins OSCin /OSCout Reference Oscillator Input/Output (Pins 1, 2) These pins form a reference oscillator when connected to terminals of an external parallel-resonant crystal. Frequency-setting capacitors of appropriate values as recommended by the crystal supplier are connected from each pin to ground (up to a maximum of 30 pF each, including stray capacitance). An external feedback resistor of 1.0 to 5.0 M is connected directly across the pins to ensure linear operation of the amplifier. The required connections for the components are shown in Figure 11. 5 M is required across the OSCin and OSCout pins in the ac-coupled case (see Figure 9 or alternate circuit Figure 10). OSCout is an internal node on the device and should not be used to drive any loads (i.e., OSCout is unbuffered). However, the buffered REFout is available to drive external loads. The external signal level must be at least 1 Vpp; the maximum frequencies are given in the Loop Specifications table. These maximum frequencies apply for R Counter divide ratios as indicated in the table. For very small ratios, the maximum frequency is limited to the divide ratio times 2 MHz. (Reason: the phase/frequency detectors are limited to a maximum input frequency of 2 MHz.) If an external source is available which swings virtually rail-to-rail (VDD to VSS), then dc coupling can be used. In the dc-coupled case, no external feedback resistor is needed. OSCout must be a No Connect to avoid loading an internal node on the device, as noted above. For frequencies below 1 MHz, dc coupling must be used. The R counter is a static counter and may be operated down to dc. However, wave shaping by a CMOS buffer may be required to ensure fast rise and fall times into the OSCin pin. See Figure 25. Each rising edge on the OSCin pin causes the R counter to decrement by one. MOTOROLA MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com 11 Pin Connections Freescale Semiconductor, Inc. REFout Reference Frequency Output (Pin 3) This output is the buffered output of the crystal-generated reference frequency or externally provided reference source. This output may be enabled, disabled, or scaled via bits in the C register (see Figure 16). REFout can be used to drive a microprocessor clock input, thereby saving a crystal. Upon power up, the onchip power-on-initialize circuit forces REFout to the OSCin divided-by-8 mode. REFout is capable of operation to 10 MHz; see the Loop Specifications table. Therefore, divide values for the reference divider are restricted to two or higher for OSCin frequencies above 10 MHz. If unused, the pin should be floated and should be disabled via the C register to minimize dynamic power consumption and electromagnetic interference (EMI). 3.3 Counter Output Pins Freescale Semiconductor, Inc... fR R Counter Output (Pin 9) This signal is the buffered output of the 15-stage R counter. fR can be enabled or disabled via the C register (patented). The output is disabled (static low logic level) upon power up. If unused, the output should be left disabled and unconnected to minimize interference with external circuitry. The fR signal can be used to verify the R counter's divide ratio. This ratio extends from 5 to 32,767 and is determined by the binary value loaded into the R register. Also, direct access to the phase detector via the OSCin pin is allowed by choosing a divide value of 1 (see Figure 17). The maximum frequency which the phase detectors operate is 2 MHz. Therefore, the frequency of fR must not exceed 2 MHz. When activated, the fR signal appears as normally low and pulses high. The pulse width is 4.5 cycles of the OSCin pin signal, except when a divide ratio of 1 is selected. When 1 is selected, the OSCin signal is buffered and appears at the fR pin. fV N Counter Output (Pin 10) This signal is the buffered output of the 16-stage N counter. fV can be enabled or disabled via the C register (patented). The output is disabled (static low logic level) upon power up. If unused, the output should be left disabled and unconnected to minimize interference with external circuitry. The fV signal can be used to verify the N counter's divide ratio. This ratio extends from 40 to 65,535 and is determined by the binary value loaded into the N register. The maximum frequency which the phase detectors operate is 2 MHz. Therefore, the frequency of fV must not exceed 2 MHz. When activated, the fV signal appears as normally low and pulses high. 3.4 Loop Pins fin Frequency Input (Pin 4) This pin is a frequency input from the VCO. This pin feeds the on-chip amplifier which drives the N counter. This signal is normally sourced from an external voltage-controlled oscillator (VCO), and is accoupled into fin. A 100 pF coupling capacitor is used for measurement purposes and is the minimum size recommended for applications (see Figure 25). The frequency capability of this input is dependent on the supply voltage as listed in Table 6, Loop Specifications. For small divide ratios, the maximum frequency is limited to the divide ratio times 2 MHz. (Reason: the phase/frequency detectors are limited to a maximum frequency of 2 MHz.) 12 MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Pin Connections For signals which swing from at least the VIL to VIH levels listed in the Electrical Characteristics table, dc coupling may be used. Also, for low frequency signals (less than the minimum frequencies shown in the Loop Specifications table), dc coupling is a requirement. The N counter is a static counter and may be operated down to dc. However, wave shaping by a CMOS buffer may be required to ensure fast rise and fall times into the fin pin. See Figure 25. Each rising edge on the fin pin causes the N counter to decrement by 1. PDout Single-Ended Phase/Frequency Detector Output (Pin 13) This is a three-state output for use as a loop error signal when combined with an external low-pass filter. Through use of a Motorola patented technique, the detector's dead zone has been eliminated. Therefore, the phase/frequency detector is characterized by a linear transfer function. The operation of the phase/ frequency detector is described below and is shown in Figure 19. POL bit (C7) in the C register = low (see Figure 16) Freescale Semiconductor, Inc... Frequency of fV > fR or Phase of fV Leading fR: negative pulses from high impedance Frequency of fV < fR or Phase of fV Lagging fR: positive pulses from high impedance Frequency and Phase of fV = fR: essentially high-impedance state; voltage at pin determined by loop filter POL bit (C7) = high Frequency of fV > fR or Phase of fV Leading fR: positive pulses from high impedance Frequency of fV < fR or Phase of fV Lagging fR: negative pulses from high impedance Frequency and Phase of fV = fR: essentially high-impedance state; voltage at pin determined by loop filter This output can be enabled, disabled, and inverted via the C register. If desired, PDout can be forced to the high-impedance state by utilization of the disable feature in the C register (patented). R and V Double-Ended Phase/Frequency Detector Outputs (Pins 14, 15) These outputs can be combined externally to generate a loop error signal. Through use of a Motorola patented technique, the detector's dead zone has been eliminated. Therefore, the phase/frequency detector is characterized by a linear transfer function. The operation of the phase/frequency detector is described below and is shown in Figure 19. POL bit (C7) in the C register = low (see Figure 16) Frequency of fV > fR or Phase of fV Leading fR: V = negative pulses, R = essentially high Frequency of fV < fR or Phase of fV Lagging fR: V = essentially high, R = negative pulses Frequency and Phase of fV = fR: V and R remain essentially high, except for a small minimum time period when both pulse low in phase POL bit (C7) = high Frequency of fV > fR or Phase of fV Leading fR: R = negative pulses, V = essentially high Frequency of fV < fR or Phase of fV Lagging fR: R = essentially high, V = negative pulses Frequency and Phase of fV = fR: V and R remain essentially high, except for a small minimum time period when both pulse low in phase These outputs can be enabled, disabled, and interchanged via the C register (patented). MOTOROLA MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com 13 Pin Connections Freescale Semiconductor, Inc. LD Lock Detector Output (Pin 11) This output is essentially at a high level with narrow low-going pulses when the loop is locked (fR and fV of the same phase and frequency). The output pulses low when fV and fR are out of phase or different frequencies (see Figure 19). This output can be enabled and disabled via the C register (patented). Upon power up, on-chip initialization circuitry disables LD to a static low logic level to prevent a false "lock" signal. If unused, LD should be disabled and left open. 3.5 Power Supply VDD Most Positive Supply Potential (Pin 16) Freescale Semiconductor, Inc... This pin may range from 2.7 to 5.5 V with respect to VSS. For optimum performance, VDD should be bypassed to VSS using low-inductance capacitor(s) mounted very close to the device. Lead lengths on the capacitor(s) should be minimized. (The very fast switching speed of the device causes current spikes on the power leads.) VSS Most Negative Supply Potential (Pin 12) This pin is usually ground. For measurement purposes, the VSS pin is tied to a ground plane. Power Up ENB CLK 1 2 3 1 2 3 4 5 4 or More Clocks Din Don't Cares Zeroes One Zero Don't Cares NOTE: This initialization sequence is usually not necessary because the on-chip power-on reset circuit performs the initialization function. However, this initialization sequence must be used immediately after power up if control of the CLK pin is not possible. That is, if CLK (Pin 7) toggles or floats upon power up, use the above sequence to reset the device. Also, use this sequence if power is momentarily interrupted such that the supply voltage to the device is reduced to below 2.7 V, but not down to at least 1 V (for example, the supply drops down to 2 V). This is necessary because the on-chip power-on reset is only activated when the supply ramps up from a voltage below approximately 1.0 V. Figure 15. Reset Sequence 14 MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Pin Connections ENB CLK 1 MSB 2 3 4 5 6 7 LSB 8 * Din C7 C6 C5 C4 C3 C2 C1 C0 * At this point, the new byte is transferred to the C register and stored. No other registers are affected. C7 - POL: Select the output polarity of the phase/frequency detectors. When set high, this bit inverts PDout and interchanges the R function with V as depicted in Figure 19. Also see the phase detector output pin descriptions for more information. This bit is cleared low at power up. C6 - PDA/B: Selects which phase/frequency detector is to be used. When set high, enables the output of phase/frequency detector A (PDout) and disables phase/frequency detector B by forcing R and V to the static high state. When cleared low, phase/frequency detector B is enabled (R and V) and phase/frequency detector A is disabled with PDout forced to the high-impedance state. This bit is cleared low at power up. C5 - LDE: Enables the lock detector output when set high. When the bit is cleared low, the LD output is forced to a static low level. This bit is cleared low at power up. Freescale Semiconductor, Inc... C4 - C2, OSC2 - OSC0: Reference output controls which determines the REFout characteristics as shown below. Upon power up, the bits are initialized such that OSCin/8 is selected. C4 0 0 0 0 1 C3 0 0 1 1 0 C2 0 1 0 1 0 REFout Frequency dc (Static Low) OSCin OSCin /2 OSCin /4 OSCin /8 (POR Default) OSCin /16 OSCin /8 OSCin /16 1 1 1 0 1 1 1 0 1 C1 - fVE: C0 - fRE: Enables the fV output when set high. When cleared low, the fV output is forced to a static low level. The bit is cleared low upon power up. Enables the fR output when set high. When cleared low, the fR output is forced to a static low level. The bit is cleared low upon power up. Figure 16. C Register Access and Format (8 Clock Cycles are Used) MOTOROLA MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com 15 Freescale Semiconductor, Inc... 16 * NB LK MSB X X X X X X X X X R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 1 2 3 11 12 15 21 6 14 17 20 4 5 10 8 13 16 19 22 7 9 18 23 24 LSB R1 R0 Pin Connections n Don't Care Bits See Below See Below See Below See Below ENB * CLK MSB Din R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 1 2 3 11 4 5 10 8 6 7 9 12 13 14 LSB R2 R1 R0 Freescale Semiconductor, Inc. Figure 17. R Register Access and Formats (Either 24 or 15 Clock Cycles Can Be Used) 15 MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com 0 0 0 0 0 0 0 0 . . . 7 7 0 0 0 0 0 0 0 0 . . . F F 0 0 0 0 0 0 0 0 . . . F F 0 1 2 3 4 5 6 7 . . . E F R Counter = /32,766 R Counter = /32,767 Decimal Equivalent Hexadecimal Value Octal Value * At this point, the new data is transferred to the R register and stored. No other registers are affected. Not Allowed R Counter = /1 (Direct Access to Reference Side of Phase/Frequency Detector) Not Allowed Not Allowed Not Allowed R Counter = /5 R Counter = /6 R Counter = /7 MOTOROLA Freescale Semiconductor, Inc. Pin Connections ENB CLK 1 MSB 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 LSB * Din N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 Freescale Semiconductor, Inc... 0 0 0 0 . . . 0 0 0 0 0 0 0 . . . F F 0 0 0 0 . . . 0 0 0 0 0 0 0 . . . F F 0 0 0 0 . . . 2 2 2 2 2 2 2 . . . F F 0 1 2 3 . . . 5 6 7 8 9 A B . . . E F Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed N Counter = /40 N Counter = /41 N Counter = /42 N Counter = /43 N Counter = /65,534 N Counter = /65,535 Decimal Equivalent Hexadecimal Value *At this point, the two new bytes are transferred to the N register and stored. No other registers are affected. In addition, the N and R counters are jam-loaded and begin counting down together. Figure 18. N Register Access and Format (16 Clock Cycles Are Used) fR Reference OSCin / R fV Feedback (fin / N * VH VL VH VL VH High Impedance VL VH VL VH VL VH VL PDout R V LD VH = High voltage level VL = Low voltage level *At this point, when both fR and fV are in phase, both the sinking and sourcing output FETs are turned on for a very short internal. NOTE: The PDout generates error pulses during out-of-lock conditions. When locked in phase and frequency, the output is high impedance and the voltage at that pin is determined by the low-pass filter capacitor. PDout, R and V are shown with the polarity bit (POL) = low; see Figure 16 for POL. Figure 19. Phase/Frequency Detector and Lock Detector Output Waveforms MOTOROLA MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com 17 Design Considerations Freescale Semiconductor, Inc. 4 Design Considerations 4.1 Crystal Oscillator Considerations The following options may be considered to provide a reference frequency to Motorola's CMOS frequency synthesizers. 4.1.1 Use of a Hybrid Crystal Oscillator Commercially available temperature-compensated crystal oscillators (TCXOs) or crystal-controlled data clock oscillators provide very stable reference frequencies. An oscillator capable of CMOS logic levels at the output may be direct or dc coupled to OSCin. If the oscillator does not have CMOS logic levels on the outputs, capacitive or ac coupling to OSCin may be used (see Figures 9 and 10). Freescale Semiconductor, Inc... For additional information about TCXOs, visit motorola.com on the world wide web. 4.1.2 Use of the On-Chip Oscillator Circuitry The on-chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source frequency. A fundamental mode crystal, parallel resonant at the desired operating frequency, should be connected as shown in Figure 20. The crystal should be specified for a loading capacitance (CL) which does not exceed 20 pF when used at the highest operating frequencies listed in Table 6, Loop Specifications. Larger CL values are possible for lower frequencies. Assuming R1 = 0 , the shunt load capacitance (CL) presented across the crystal can be estimated to be: CC in out C1 C2 C L = ----------------------------- + C a + C stray + --------------------C in + C out C1 + C2 where Cin = 5.0 pF (see Figure 21) Cout = 6.0 pF (see Figure 21) Ca = 1.0 pF (see Figure 21) C1 and C2 = external capacitors (see Figure 21) Cstray = the total equivalent external circuit stray capacitance appearing across the crystal terminals The oscillator can be "trimmed" on-frequency by making a portion or all of C1 variable. The crystal and associated components must be located as close as possible to the OSCin and OSCout pins to minimize distortion, stray capacitance, stray inductance, and startup stabilization time. Circuit stray capacitance can also be handled by adding the appropriate stray value to the values for Cin and Cout. For this approach, the term Cstray becomes 0 in the above expression for CL. A good design practice is to pick a small value for C1, such as 5 to 10 pF. Next, C2 is calculated. C1 < C2 results in a more robust circuit for start-up and is more tolerant of crystal parameter variations. Power is dissipated in the effective series resistance of the crystal, Re, in Figure 22. The maximum drive level specified by the crystal manufacturer represents the maximum stress that the crystal can withstand without damage or excessive shift in operating frequency. R1 in Figure 20. limits the drive level. The use of R1 is not necessary in most cases. 18 MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Design Considerations To verify that the maximum dc supply voltage does not cause the crystal to be overdriven, monitor the output frequency at the REFout pin (OSCout is not used because loading impacts the oscillator). The frequency should increase very slightly as the dc supply voltage is increased. An overdriven crystal decreases in frequency or becomes unstable with an increase in supply voltage. The operating supply voltage must be reduced or R1 must be increased in value if the overdriven condition exists. The user should note that the oscillator start-up time is proportional to the value of R1. Through the process of supplying crystals for use with CMOS inverters, many crystal manufacturers have developed expertise in CMOS oscillator design with crystals. Discussions with such manufacturers can prove very helpful (see Table 8). Frequency Synthesizer Freescale Semiconductor, Inc... OSCin Rf R1* OSCout C1 5.0 to 10 pF C2 * May be needed in certain cases. See text. Figure 20. Pierce Crystal Oscillator Circuit Ca OSCin Cin Cstray Cout OSCout Figure 21. Parasitic Capacitances of the Amplifier and Cstray RS 1 2 1 LS CS 2 CO 1 Re Xe 2 NOTE: Values are supplied by crystal manufacturer (parallel resonant crystal). Figure 22. Equivalent Crystal Networks MOTOROLA MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com 19 Design Considerations Freescale Semiconductor, Inc. Recommended Reading Technical Note TN-24, Statek Corp. Technical Note TN-7, Statek Corp. E. Hafner, "The Piezoelectric Crystal Unit-Definitions and Method of Measurement", Proc. IEEE, Vol. 57, No. 2, Feb. 1969. D. Kemper, L. Rosine, "Quartz Crystals for Frequency Control", Electro-Technology, June 1969. P. J. Ottowitz, "A Guide to Crystal Selection", Electronic Design, May 1966. D. Babin, "Designing Crystal Oscillators", Machine Design, March 7, 1985. D. Babin, "Guidelines for Crystal Oscillator Design", Machine Design, April 25, 1985. Contact Motorola for MC145170-2 control software. Freescale Semiconductor, Inc... Table 8. Partial List of Crystal Manufacturers CTS Corp. United States Crystal Corp. Crystek Crystal Statek Corp. Fox Electronics NOTE: Motorola cannot recommend one supplier over another and in no way suggests that this is a complete listing of crystal manufacturers. 20 MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Design Considerations (A) PDout VCO R1 KK VCO ------------------------NR C 1 N n = ----------------------------2K K VCO n = C 1 F ( s ) = ------------------------R sC + 1 1 (B) PDout VCO R1 R2 C n = KK VCO -----------------------------------NC ( R + R ) 1 2 N = 0.5 R C + ------------------------- n 2 KK VCO R 2 sC + 1 F ( s ) = -------------------------------------------( R 1 + R 2 )sC + 1 Freescale Semiconductor, Inc... (C) R1 R2 R V + R1 R2 C A MC33077 or equivalent (Note 3) C VCO n = KK VCO ------------------------NCR 1 n R2 C = -------------------2 R sC + 1 2 F ( s ) = ------------------------R sC 1 Notes: 1. For (C), R1 is frequently split into two series resistors; each resistor is equal to R1 divided by 2. A capacitor CC is then placed from the midpoint to ground to further filter the error pulses. The value of CC should be such that the corner frequency of this network does not significantly affect n. 2. The R and V outputs swing rail-to-rail. Therefore, the user should be careful not to exceed the common mode input range of the op amp. 3. For the latest information on MC33077 or equivalent, see the Motorola IC web site at http://www.motorola.com/semiconductors. Denifitions: N = Total Division Ratio in Feedback Loop K (Phase Detector Gain) = VDD/4p volts per radian for PDout K (Phase Detector Gain) - VDD/2p volts per radian for fV and fR For a nominal design starting point, the user might consider a damping factor = 0.7 and a natural loop frequency n = (2fR/50) where fR is the frequency at the phase detector input. Larger n values result in faster loop lock times and, for similar sideband filtering, higher fR-related VCO standards. Figure 23. Phase-Locked Loop - Low Pass Filter Design 2fVCO K VCO ( VCO Gain ) = ------------------------V VCO MOTOROLA MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com 21 Design Considerations Freescale Semiconductor, Inc. VHF Output Buffer VHF VCO Low-pass Filter V+ 1 OSC in 2 OSC out 4 5 6 MC145170-2 VDD 16 V 15 R 14 PDout 13 Optional Loop Error Signals (Note 1) V+ 3 REF fin Din ENB CLK VSS 12 LD 11 fV 10 fR 9 Freescale Semiconductor, Inc... MCU Optional 7 8D out Threshold Detector Optional (Note 5) Integrator (Note 4) NOTES: 1. The R and V outputs are fed to an external combiner/loop filter. See the Phase-Locked Loop -- Low-Pass Filter Design page for additional information. The R and V outputs swing rail-to-rail. Therefore, the user should be careful not to exceed the common mode input range of the op amp used inthe combiner/loop filter. 2. For optimum performance, bypass the VDD pin to VSS (GND) with one or more low-inductance capacitors. 3. The R counter is programmed for a divide value = OSCin/fR. Typically, fR is the tuning resolution required for the VCO. Also, the VCO frequency divided by fR = N, wher e N is the divide value of the N counter. 4. May be an R-C low-pass filter. 5. May be a bipolar transistor. Figure 24. Example Application 22 MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Design Considerations V+ 14 A 1 2 C OSCin VDD OSCout MC145170-2 No Connect MC74HC14A B 3 4 D fin 7 VSS Freescale Semiconductor, Inc... NOTE: The signals at Points A and B may be low-frequency sinusoidal or square waves with slow edge rates or noisy signal edges. At Points C and D, the signals are cleaned up, have sharp edge rates, and rail-to-rail signal swings. With signals as described at Points C and D, the MC145170-2 is guaranteed to operate down to a frequency as low as dc. Refer to the MC74HC14A data sheet for input switching levels and hysteresis voltage range. Figure 25. Low Frequency Operation Using DC Coupling MOTOROLA MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com 23 Design Considerations Freescale Semiconductor, Inc. (Pin 4) f in SOG Package 1 2 3 4 Freescale Semiconductor, Inc... Marker 1 2 3 4 Frequency (MHz) 5 100 150 185 Resistance () 2390 39.2 25.8 42.6 Reactance () -5900 -347 -237 -180 Capacitance (pF) 5.39 4.58 4.48 4.79 Figure 26. Input Impedance at fin - Series Format (R + jX) (5.0 MHz to 185 MHz) Device #1 MC145170-2 Din CLK ENB Dout Din Device #2 MC145170-2 CLK ENB Dout 33 k NOTE 1 CMOS MCU Optional NOTES: 1. The 33 k resistor is needed to prevent the Din pin from floating. (The Dout pin is a three-state output.) 2. See related Figures 28, 29, and 30. Figure 27. Cascading Two MC145170-2 Devices 24 MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc... 25 7 8 9 33 34 10 24 39 15 17 32 18 25 16 23 31 26 40 NOTE X X X X C7 C6 C0 X X X C7 C6 C0 C Register Bits of Device #2 in Figure 27 C Register Bits of Device #1 in Figure 27 ENB CLK 1 2 Din X X NOTE: At this point, the new data is transferred to the C registers of both devices and stored. No other registers are affected. Figure 28. Accessing the C Registers of Two Cascaded MC145170-2 Devices ENB CLK 1 25 26 30 27 31 39 2 8 9 10 NOTE 40 41 42 44 45 48 49 50 55 56 Freescale Semiconductor, Inc. MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com X X R14 R13 R9 R1 R0 X R14 R11 R Register Bits of Device #2 in Figure 27 Din X X R7 R6 R0 R Register Bits of Device #1 in Figure 27 NOTE: At this point, the new data is transferred to the R registers of both devices and stored. No other registers are affected. MOTOROLA Figure 29. Accessing the R Registers of Two Cascaded MC145170-2 Devices Freescale Semiconductor, Inc... 26 NOTE 8 15 16 17 25 31 32 33 39 47 40 41 24 23 9 10 48 X X X N15 N8 N7 N0 N15 N8 N7 N0 N Register Bits of Device #2 in Figure 27 N Register Bits of Device #1 in Figure 27 ENB CLK 1 2 Din X X NOTE: At this point, the new data is transferred to the N registers of both devices and stored. No other registers are affected. Freescale Semiconductor, Inc. MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com Figure 30. Accessing the N Registers of Two Cascaded MC145170-2 Devices MOTOROLA Freescale Semiconductor, Inc. Design Considerations V+ VPD VDD Device #1 MC145170-2 Din CLK ENB Dout VDD VCC Device #2 Note 2 VPD Output A (Dout) Din CLK ENB 33 k Note 1 CMOS MCU Optional Freescale Semiconductor, Inc... NOTES: 1. The 33 k resistor is needed to prevent the Din pin from floating. (The Dout pin is a three-state output.) 2. This PLL Frequency Synthesizer may be a MC145190, MC145191, MC145192, MC145200, or MC145201. 3. See related Figures 32, 33, and 34. Figure 31. Cascading Two Different Device Types MOTOROLA MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com 27 Freescale Semiconductor, Inc... 28 7 8 9 10 15 16 17 18 23 24 25 26 31 32 33 34 39 40 NOTE X X X X C7 C6 C0 X X X C7 C6 C0 C Register Bits of Device #2 in Figure 31 C Register Bits of Device #1 in Figure 31 ENB CLK 1 2 Din X X NOTE: At this point, the new data is transferred to the C registers of both devices and stored. No other registers are affected. Figure 32. Accessing the C Registers of Two Different Device Types ENB NOTE 16 20 21 30 22 31 32 17 18 39 40 41 42 43 46 47 48 55 56 CLK 1 2 Freescale Semiconductor, Inc. MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com A23 A9 A22 A19 A18 A8 A0 X R14 R13 A Register Bits of Device #2 in Figure 31 Din X X R9 R8 R0 R Register Bits of Device #1 in Figure 31 NOTE: At this point, the new data is transferred to the A register of Device #2 and R register of Device #1 and stored. No other registers are affected. MOTOROLA Figure 33. Accessing the A and R Registers of Two Different Device Types Freescale Semiconductor, Inc... 29 8 15 16 39 40 41 47 17 23 24 25 31 33 32 9 10 48 NOTE X X X R15 R8 R7 R0 N15 N8 N7 N0 R Register Bits of Device #2 in Figure 31 N Register Bits of Device #1 in Figure 31 ENB CLK 1 2 Din X X NOTE: At this point, the new data is transferred to the R register of Device #2 and N register of Device #1 and stored. No other registers are affected. Freescale Semiconductor, Inc. MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com Figure 34. Accessing the R and N Registers of Two Different Device Types MOTOROLA Packaging Freescale Semiconductor, Inc. 5 Packaging -A16 9 B 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0 10 _ _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0 10 _ _ 0.51 1.01 F S C L -TH G D 16 PL SEATING PLANE K J M Freescale Semiconductor, Inc... 0.25 (0.010) M T A M DIM A B C D F G H J K L M S Figure 35. Outline Dimensions for P Suffix, DIP-16 (Case 648-08, Issue R) 0.25 PIN'S NUMBER 1 8X M B A 6.2 5.8 16 1.75 1.35 0.25 0.10 16X 0.49 0.35 0.25 6 M TAB PIN 1 INDEX 14X 1.27 10.0 9.8 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS A AND B TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS, MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTER-LEAD FLASH OR PROTRUSIONS. INTER-LEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.62 MM. 4 A A 8 9 T 4.0 3.8 5 B 16X SEATING PLANE 0.1 T 0.50 0.25 X45 0.25 0.19 1.25 0.40 SECTION A-A 7 0 Figure 36. Outline Dimensions for D Suffix, SOG-16 (Case 751B-05, Issue J) 30 MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. A -P- Packaging 16x K REF M 0.200 (0.008) T 16 9 L PIN 1 IDENTIFICATION 1 8 B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM PLANE -U-. MILLIMETERS MIN MAX --5.10 4.30 4.50 --1.20 0.05 0.25 0.45 0.55 0.65 BSC 0.22 0.23 0.09 0.24 0.09 0.18 0.16 0.32 0.16 0.26 6.30 6.50 0 5 10 5 INCHES MIN MAX --- 0.200 0.169 0.177 --0047 0.002 0.010 0.018 0.022 0.026 BSC 0.009 0.010 0.004 0.009 0.004 0.007 0.006 0.013 0.006 0.010 0.248 0.256 0 5 10 5 Freescale Semiconductor, Inc... C 0.100 (0.004) M -U- -T- D G H SEATING PLANE K J1 J A K1 A M DIM A B C D F G H J J1 K K1 L M SECTION A-A F Figure 37. Outline Dimensions for DT Suffix, TSSOP-16 (Case 948C-03, Issue B) MOTOROLA MC145170-2 Technical Data For More Information On This Product, Go to: www.freescale.com 31 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, TECHNICAL INFORMATION CENTER: 1-800-521-6274 affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. HOME PAGE: http://www.motorola.com/semiconductors Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. (c) Motorola, Inc. 2003 MC145170-2/D For More Information On This Product, Go to: www.freescale.com |
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